Dennemeyer Octimine

Power management patents

Laura HorcajadaLaura Horcajada

Device and method of power management for graphic processing unit

Disclosed are a graphic processing unit, a power management device, and a power management method for the same. The power management device comprises a target frame number determining part configured to determine a target frame number which the GPU is required to process in a time period; a processed frame number determining part configured to determine a processed frame number processed by the GPU in a previous time period; and an operating frequency adjusting part configured to calculate a loss frame number based on the target frame number and the process frame number, and adjust an operating frequency of the GPU based on the loss frame number.

Publication number: US2015015589A1 | Search similar patents

Power management method for graphic processing unit and system thereof

Disclosed is a power management system that performs power management of a graphic processing unit (GPU). The power management system includes a dynamic voltage and frequency scaling (DVFS) driver configured to include an interface that calls a device driver of the GPU or is called by the device driver, and control an operating voltage and/or an operating frequency of the GPU, and a DVFS governor interface module configured to provide an interface for the DVFS driver to a power management policy module of an operating system (OS). Therefore, in the power management system according to the present invention, a power management policy of the OS based on a change in a workload of the GPU may be applied to the GPU, independently of a hardware configuration of the GPU.

Publication number: US2014146060A1 | Search similar patents

Electronic systems including heterogeneous multi-core processors and methods of operating same

A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

Publication number: US2015121105A1 | Search similar patents

Monte carlo simulation using gpu units on personal computers

A method of performing a Monte Carlo analysis uses a graphical processor unit (415) of a computer system. Individual data sets to be analyzed are allocated to respective pixel locations in a graphical processor unit memory (425) for Monte Carlo simulation and the outcome of the Monte Carlo simulation is calculated for each data set using stream processing in the graphical processor unit (415).

Publication number: EP1865430A2 | Search similar patents

Electronic device, and control method therefor

An electronic device is disclosed. The electronic device comprises: a dynamic voltage and frequency scaling (DVFS) unit for measuring the usage of an application processor (AP) corresponding to at least one function being executed and for controlling the voltage and operating frequency of the AP on the basis of the measured AP usage; and a control unit for controlling the DVFS unit not to control the voltage and operating frequency of the AP if said at least one function includes a preset function. Accordingly, if the preset function is executed, the response speed can be increased by not controlling the voltage and operating frequency of the AP.

Publication number: WO2016060457A2 | Search similar patents

System-on-chip performing dynamic voltage and frequency scaling

A system-on-chip (SoC), measures the workload of a graphics processing unit (GPU), compares the frame process speed of the GPU with the frame rate of a display device, and adjusts the operating frequency of the GPU based on the comparison result and the workload of the GPU.

Publication number: US2014184619A1 | Search similar patents

System, method, and computer program product for a tessellation engine using a geometry shader

A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.

Publication number: EP2289000A1 | Search similar patents

Execution of graphics and non-graphics applications on a graphics processing unit

The techniques described in this disclosure are directed to efficient parallel execution of graphics and non-graphics application on a graphics processing unit (GPU). The GPU may include a plurality of shader cores within a shader processor. The techniques may reserve one or more shader cores to execute the graphics application and reserve one or more other shader cores to execute the non-graphics application. In this manner, the execution of the non-graphics application may not interfere with the execution of the graphics application, and vice-versa.

Publication number: WO2013133957A1 | Search similar patents

Method and computer-readable medium for dynamically managing power of multi-core processor


A method and a computer-readable medium (150) for dynamically managing power of a multi-core processor (100) of a computing system (10) are provided. The multi-core processor (100) generates a dynamic voltage and frequency scaling (DVFS) table (200, 3001 to 3008), determines a first index (230) by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) (202) of the computing system (10), selects one of entries (204) according to the current TLP (202) and the first index (230), and configure first cores 110) and second cores (120) thereof according to a first settings (210) and a second settings (220) of the selected entry (204).

Publication number: EP2990909A1 | Search similar patents

Application processor and dynamic thermal management method thereof

Provided is a dynamic thermal management method performed by an application processor which stores a first dynamic voltage and frequency scaling (DVFS) table and a second DVFS table, the method including comparing a surface temperature of a mobile apparatus with a critical surface temperature, controlling performance of the application processor according to the first DVFS table when the surface temperature is less than the critical surface temperature, and controlling performance of the application processor according to the second DVFS table when the surface temperature is not less than the critical surface temperature.

Publication number: US2014324245A1 | Search similar patents

Address independent shader program loading

A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Publication number: US9024957B1 | Search similar patents

System and method for power optimization

A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.

Publication number: US2011213998A1 | Search similar patents

Dual-Rail Power Equalizer

A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Publication number: US2016320821A1 | Search similar patents

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