Logic circuits using carbon nanotube transistors
In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
Publication number: US2008143389A1 | Search similar patents
Complementary carbon nanotube triple gate technology
Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.
Publication number: US7492015B2 | Search similar patents
Field-effect transistor structure and fabrication method thereof
A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes
Publication number: US2009250731A1 | Search similar patents
Gate-all-around carbon nanotube transistor with selectively doped spacers
A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess may be between one or more contacts formed on the substrate separated by a gap.
Publication number: US8609481B1 | Search similar patents
Differential amplifier sensor architecture for increased sensing selectivity
A differential amplifier and method of sensing includes a first carbon nanotube field effect transistor (CNTFET) that selectively detects an analyte from an environment comprising analytes and nonspecific interferences, and produces a first signal associated with the detected analyte and any nonspecific interferences; a second CNTFET adjacent to the first CNTFET, wherein the second CNTFET detects the nonspecific interferences of the environment, and produces a second signal associated with the detected nonspecific interferences; and means for generating a differential output signal using the first signal and the second signal as input, wherein the differential output signal is completely devoid of the second signal.
Publication number: US2011024305A1 | Search similar patents
Transistors from vertical stacking of carbon nanotube thin films
A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region.
Publication number: US2014138623A1 | Search similar patents
Semiconductor device with ballistic gate length structure
Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.
Publication number: US2015194619A1 | Search similar patents
Biosensor and system and process for forming
A process for forming a carbon nanotube field effect transistor (CNTFET) device includes site-specific nanoparticle deposition on a CNTFET that has one or more carbon nanotubes, a source electrode, a drain electrode, and a sacrificial electrode on a substrate with an interposed dielectric layer. The process includes control of PMMA removal and electrodeposition in order to select nanoparticle size and deposition location down to singular nanoparticle deposition. The CNTFET device resulting in ultra-sensitivity for various bio-sensing applications, including detection of glucose at hypoglycemic levels.
Publication number: US8895340B1 | Search similar patents
Vertical carbon nanotube-field effect transistor and method of manufacturing the same
Provided are a vertical carbon nanotube field effect transistor (CNTFET) and a method of manufacturing the same. The method includes: forming a first electrode on a substrate; forming a stack of multiple layers (“multi-layer stack”) on the first electrode, the multiple layers including first and second buried layers and a sacrificial layer interposed between the first and second buried layers; forming a vertical well into the multi-layer stack; growing a CNT within the well; forming a second electrode connected to the CNT on the multi-layer stack into which the well has been formed; forming a protective layer on the second electrode; removing the sacrificial layer and exposing the CNT between the first and second buried layers; forming a gate insulating layer on the exposed surface of the CNT; and forming a gate enclosing the CNT on the gate insulating layer. The CNTFET and manufacturing method maximize the effect of electric field produced by the gate due to the channel completely enclosed by the gate while improving a ratio Ion/Ioff of on-current to off-current by fully depleting a depletion layer formed in the channel.
Publication number: US2005156203A1 | Search similar patents
Tunneling nanotube field effect transistor and manufacturing method thereof
A tunneling nanotube field effect transistor includes: an insulating layer disposed on a substrate; a gate electrode disposed on the insulating layer; a source electrode and a drain electrode disposed on the insulating layer on respective adjacent sides of the gate electrode; and a carbon nanotube extending through the gate electrode, wherein the carbon nanotube is supported by the source electrode, the gate electrode, and the drain electrode, wherein the carbon nanotube includes a first portion adjacent to the source electrode and a second portion adjacent to the drain electrode, and wherein the source electrode and the gate electrode are spaced apart by an exposed section of the first portion, and the drain electrode and the gate electrode are spaced apart by an exposed section of the second portion.
Publication number: US2015318504A1 | Search similar patents
Shared gate for conventional planar device and horizontal cnt
A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
Publication number: US2007021293A1 | Search similar patents
Passivation of carbon nanotubes with molecular layers
A transistor device includes an insulator on a substrate and a gate embedded in the insulator. The transistor device further includes a dielectric material, a channel, and a self-assembled monolayer. The dielectric material is deposited over the gate and insulator forming a dielectric layer. The channel includes carbon nanotubes and is formed on the dielectric layer over the gate. The self-assembled monolayer is formed over at least the channel.
Publication number: US2014001542A1 | Search similar patents
Carbon nanotube, method for positioning the same, field-effect transistor made using the carbon nanotube, method for making the field-effect transistor, and semiconductor device
Carbon nanotube, method for positioning the same, field effect transistor made using the carbon nanotube, method for making the field-effect transistor, and a semiconductor device are provided. The carbon nanotube includes a bare carbon nanotube and a functional group introduced to at least one end of the bare carbon nanotube.
Publication number: US7601322B2 | Search similar patents
Cnt-based electronic and photonic devices
The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.
Publication number: US2013146836A1 | Search similar patents
Self-aligned nano field-effect transistor and its fabrication
Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can be adjusted to satisfy the requirements of large scale integrated circuit.
Publication number: US2010090293A1 | Search similar patents